H4 Bus Interface Timing

Question:
What speed memory devices are needed to run code on the XA-H4 with no wait states? The XA-H4 is running at 29.4912 MHz using an external crystal.

Answer:
There are three timing numbers that must be accounted for when determining the required access time for the XA-H4 code space devices. The first is the Address to Data valid time for a standard code fetch, with no wait states. This access requires 3 clock cycles minus the Address Output delay and the Data Setup time. Referring to the diagram below, this would correspond to the equation:
3*TC – TCHAV - TDIS. 

Using the values from the XA-H4 Data Sheet yields:
3*34 - 25 - 25 = 52ns at 5V or
3*34 - 30 - 32 = 40ns at 3.3V.


The second number to calculate is the Output Enable to Data valid time. This value is calculated as 2 clock cycles minus the Chip Select Output delay and the Data Setup time. Referring to the diagram below, this would correspond to the equation: 
2*TC – TCHSL - TDIS. 

Using the values from the XA-H4 Data Sheet yields:
2*34 - [1->19] - 25 = 24->42ns at 5V or
2*34 - [1->25] - 32 = 11->35ns at 3.3V.


The Final number to determine is the Address to Data valid time for a burst code fetch, with no wait states. This access takes one clock less that the standard code fetch, so the access requires 2 clock cycles minus the Address Output delay and the Data Setup time. Referring to the diagram below, this would correspond to the equation: 
2*TC – TCHAV - TDIS. 

Using the values from the XA-H4 Data Sheet yields:
2*34 - 25 - 25 = 18ns at 5V or
2*34 - 30 - 32 = 6ns at 3.3V.

From these numbers, the code device would need an Address to Data valid time of 18ns (or 6 ns at 3.3V) and an Output enable to Data valid time of 24ns (or 11 ns at 3.3V). The only devices currently available with these access times are high-speed SRAM devices. In order to use a typical Flash part (access times of 70ns), two extra clock cycles will have to be inserted into each access. This would add 2*TC (or 68ns) to each of the above numbers and would give an Address to Data valid time of 86ns (or 74 ns at 3.3V) and an Output enable to Data valid time of 92ns (or 79 ns at 3.3V).





From the XA-H4 data sheet, an XA-H4 running at 29.4912 MHz would have the following timing parameters:
TC = 34ns
TCHAV = 25ns (30ns at 3.3V)
TCHSL = 1-19ns (1-25ns at 3.3V)
TDIS = 25ns (32ns at 3.3V)