XA External Bus Timing Calculator 
for the XA-S37 and XA-G37 at 3v
Copyright 2000, 2001

Enter Clock frequency (in MHz): (mhz)

3v / 5v
   Clock Period (t):
     seconds
 or nanoseconds

BTRL
WM1 WM0 ALEW N/A CR1 CR0 CRA1 CRA0
BTRH
DW1 DW0 DWA1 DWA0 DR1 DR0 DRA1 DRA0

   

   

 

 

Programmable Variables (in clock cycles)
Variable w/ ALE w/o ALE

Description
V1
ALEW + 0.5		 N/A ALE Pulse Width
V2
2 + (2 * CRA1) + CRA0 - (V1 + 0.5)
1 + (2 * CR1) + CR0		 
PSEN Pulse Width
V3
2 + (2 * CRA1) + CRA0		 N/A 
Code Read Cycle with ALE
V4 N/A
1 + (2 * CR1) + CR0		 
Code Read Cycle without ALE
V5 N/A
1 + (2 * DR1) + DR0		 
Data Read without ALE
V6
2 + (2 * DRA1) + DRA0		 N/A 
Data Read with ALE
V7
2 + (2 * DRA1) + DRA0 - (v1 + 0.5)
1 + (2 * DR1) + DR0		 Read Pulse Width
V8
WM1 + 1
WM1 + 1		 Write Pulse Width
V9
2 + (2 * DWA1) + DWA0 - V8 - WM0 - v1
2 + (2 * DW1) + DW0 - v8 - WM0		 Write Setup Time
V10 N/A N/A Bus Strobe Length for Wait
V11
WM0
WM0		 Write Hold Time
V12
2 + (2 * DWA1) + DWA0 - V8 - WM0 - v1		 N/A ALE to Write Delay
V13
2+(2 * DWA1) + DWA0 - V8 - WM0 - (v1+ 0.5)
2 + (2 * DW1) + DW0 - v8 - WM0		 Write Setup Time

 

 

Address Cycle
 
t LHLL ALE Pulse Width MIN
(t * V1) - 6
t AVLL Address valid to ALE-de-asserted (setup) MIN
(t * V1) - 12
t LLAX Address hold after ALE de-asserted MIN
 (t/2) - 10

 

Code Read Cycle
      w/ ALE w/o ALE
t PLPH PSEN pulse width MIN
(t * V2) - 10  
(t * V2) - 10  
t LLPL ALE de-asserted to PSEN asserted MIN
(t/2) -7		 N/A
t AVIVA Address valid to instruction valid (ALE) access time MAX
(t * V3) - 36		 N/A
t AVIVB Address valid to instruction valid (non ALE) access time MAX N/A
(t * V4) - 29
t PLIV PSEN asserted to instruction valid (enable time) MAX
(t * V2) - 29
(t * V2) - 29

 

Data Read Cycle
  w/ ALE w/o ALE
t RLRH -RD pulse width  MIN
(t * V7) - 10
(t * V7) - 10
t LLRL ALE de-asserted to -RD asserted  MIN
(t/2) - 7		 N/A
t AVDVA Address valid to data input valid, ALE access time  MAX
(t * V6) - 36		 N/A
t AVDVB Address valid to data input valid, non-ALE access time  MAX N/A
(t * V5) - 29
t RLDV -RD low to valid data in (enable time) MAX
(t * V7) - 29
(t * V7) - 29

 

Data Write Cycle
  w/ ALE w/o ALE
t WLWH -WR pulse width MIN
(t * V8) - 10
(t * V8) - 10
t LLWL ALE falling edge to -WR asserted MIN
(t * V12) - 10		 N/A
t QVWX Data valid before -WR asserted (data setup time) MIN
(t * V13) - 22
(t * V13) - 22
t WHQX Data hold time after -WR de-asserted MIN
(t * V11) - 5
(t * V11) - 5
t AVWL Address valid to -WR asserted (setup time) MIN
(t * V9) - 22
(t * V9) - 22
t UAWH Hold time of unlatched address after -WR de-asserted MIN
(t * V11) - 29
(t * V11) - 7

 

Wait Input
t WTH WAIT stable after - WR strobe assertion MAX
(t * V9) - 3 0
t WTL WAIT hold after - WR strobe assertion MIN
(t * V8) - 5

 

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